Overview

This project explores a fully discrete, purely analog buck converter designed to remain stable under highly dynamic loads, while intentionally removing two common stabilizers: a fixed PWM clock and an output capacitor.

The switching frequency is not fixed; it emerges naturally from the loop dynamics and adapts in real time as operating conditions change.

Motivation

Conventional buck converters rely on fixed PWM clocks and large output capacitors to absorb load transients and mask control limitations. This project investigates whether fast, clean analog feedback can react quickly enough that bulk output capacitance becomes optional in certain dynamic scenarios.

The objective is not minimalism for its own sake, but to understand how much stability can be achieved when the loop response is allowed to dominate system behavior.

Problem Definition & Constraints

• No digital control (no firmware, no microcontroller, no DSP)
• No fixed PWM clock or external timing reference
• No output capacitor used for stabilization
• Stability required under extreme load transitions

Architectural Approach

The converter is implemented as a discrete current-mode buck. Operational amplifiers are used only for analog comparison and conditioning; no dedicated control ICs or timers are present.

Switching behavior is governed entirely by the feedback loop, allowing frequency and duty behavior to self-adjust based on instantaneous operating conditions.

For early validation, the simulated design uses a P-channel MOSFET as the high-side switch. This simplifies gate-drive requirements and keeps the focus on loop dynamics and current-mode behavior.

The architecture is not dependent on P-channel devices. An equivalent implementation using an N-channel MOSFET is entirely feasible, but would require additional high-side drive or level-shifting circuitry. The control concept itself is independent of device polarity.

Architecture Overview

• Power stage (switching element, inductor, freewheel path)
• Current sensing for cycle-level energy control
• Error and comparison stage defining switching thresholds
• Gate behavior derived directly from loop dynamics

Detailed component values and internal thresholds are intentionally abstracted.

Simulation Results

The design was evaluated in LTspice across extreme load transitions to assess transient response and stability. Switching frequency adapts naturally as a function of loop behavior.

Early Hardware Exploration

An initial hardware build was attempted to explore practical feasibility and to expose timing, noise, and parasitic effects not captured in simulation.

This early attempt highlighted the sensitivity of the analog loop to layout, component placement, and gate-drive timing, motivating a more staged hardware approach.

Challenges & Debugging

• Initial oscillations obtained only after the circuit has been properly set up
• Replacing external timing with feedback-based switching required threshold tuning
• Next challenge: validating timing precision under real parasitics

Current Limitations

• Behavior validated in simulation only
• Parasitics, noise, and layout effects not yet characterized
• Performance claims limited to tested scenarios

Future Work

• Revised hardware proof-of-concept build
• Measurement of current-sensing fidelity under noise
• Stability margin characterization across operating range
• Comparison against clocked designs under identical tests

What I Learned

• Clean current-mode feedback can reduce reliance on bulk output capacitance
• Overshoot is primarily a loop-design problem, not an inevitability
• Allowing timing to emerge naturally reshapes ripple behavior
• Capless stability requires response faster than instability onset

What This Project Demonstrates

• Analog control design under intentionally harsh constraints
• Iterative loop tuning and failure-mode awareness
• Comfort with unconventional architectures without overclaiming